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Home Events Events Archive 2012 CS 201: Electronic Design Automation in the 21st Century: Challenges at the Design and Manufacturing Interface, ANDRES TORRES, Mentor Graphics

CS 201: Electronic Design Automation in the 21st Century: Challenges at the Design and Manufacturing Interface, ANDRES TORRES, Mentor Graphics

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What
  • Seminar
When Mar 01, 2012
from 04:15 PM to 05:45 PM
Where 3400 Boelter Hall
Contact Name
Contact Phone 310-825-4033
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Electronic Design Automation in the 21st Century: Challenges at the Design and Manufacturing Interface

Andres Torres

Mentor Graphics

Abstract:

This talk describes some of the open challenges in physical design, verification and manufacturing that need to be addressed to continue the profitable march towards smaller feature size. We are in the 7th sub-wavelength manufacturing node and moving forward manufacturing will depend more in computer science majors in all areas of the electronic design flow.

Some of the challenges will include:

1) Data stream and data synch of 4GB/sec in direct write machines

2) Examples where fast linear solvers are needed and their application in manufacturing

3) 2 and 3 Color assignments in the presence of density, and number of cut constraints

4) Color-aware routing techniques.

5) Machine learning applications in Physical verifications


Bio:

Andres Torres holds a B.S. in Chemical Engineering from the National Autonomous University of Mexico, a M.S. in Chemical Engineering from UW-Madison and a PhD degree in Electrical Engineering from the Oregon Graduate Institute. He has been investigating the interactions between manufacturing process and electronic design flows to exploit areas of design and process co-optimization that provide more predictable and manufacturable designs. He has been with Mentor Graphics’ Design-to-silicon division since 2001 working in the areas of Resolution Enhancement Technologies, Design for Manufacturing and Process Hardening Layout Techniques. He has published over fifty papers and holds five patents in the area of semiconductor manufacturing. He is currently the Product Lead Engineer of the Litho Friendly Design group in the Design to Silicon Division.


Hosted by Prof Jason Cong

 

DATE:  Thursday, March 1

 

** Refreshments at 3:45 pm, Speaker at 4:15pm **

 

TIME:  4:15 – 5:45 P.M.

 

PLACE: 3400 Boelter Hall

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